Developer Interface

Constructors

uhdl.randbits(n)

uhdl.Sig(val=None, w=None, min=None, max=None)

uhdl.create(n, constructor, *args, **kwargs)

Helper function for constructing multiple objects with the same arguments.

Shorthand for [constructor(*args, **kwargs) for i in range(n)]

uhdl.Sigs(n, *args, **kwargs)

Create multiple Signals cleanly.

Parameters:

• n – number of signals to create.
• *args – passed through to Sig()
• **kwargs – passed through to Sig()

Returns:

[Sig(*args, **kwargs) for i in range(n)]

Simulation

class uhdl.HW(top, *args, **kwargs)

A Hardware module.

Provides a uniform API for conversion and simulation of MyHDL Instances.

config

dict

Dictionary(CaselessDict) containing the default config.

Modifying this attribute will change the default argument values of the convert() and sim() methods.

convert(**kwargs)

Converts the top function to another HDL

Note

VHDL conversion has not been implemented yet.

Parameters:

• hdl (str, optional) – The target language. Defaults to ‘verilog’.
• path (str, optional) – Destination folder. Defaults to current dir.
• name (str, optional) – Top level instance name, and output file name. Defaults to self.top.__name__
• tb (bool, optional) – Specifies whether a test bench should be created. Defaults to True.
• trace (bool, optional) – Whether the testbench should dump all signal waveforms. Defaults to True.
• timescale (str, optional) – Defaults to ‘1ns/1ps’

sim(**kwargs)

Simulate the top function.

Parameters:

• backend (str, optional) – Simulation runner. Available options are ‘myhdl’, ‘icarus’ and ‘modelsim’. Defaults to ‘myhdl’.
• hdl (str) – Target HDL for conversion before simulation.
• **kwargs – Optional arguments that convert() takes.

Returns:

Generator sequence if the backend is myhdl,

myhdl.Cosimulation object if the backend is a simulator.