UHDL: Python Hardware Description for Humans.¶
Contents:
Installation¶
At the command line:
$ easy_install uhdl
Or, if you have virtualenvwrapper installed:
$ mkvirtualenv uhdl
$ pip install uhdl
Developer Interface¶
Constructors¶
Simulation¶
-
class
uhdl.
HW
(top, *args, **kwargs)[source]¶ A Hardware module.
Provides a uniform API for conversion and simulation of MyHDL Instances.
-
config
¶ dict
Dictionary(
CaselessDict
) containing the default config.Modifying this attribute will change the default argument values of the
convert()
andsim()
methods.
-
convert
(**kwargs)[source]¶ Converts the top function to another HDL
Note
VHDL conversion has not been implemented yet.
Parameters: - hdl (str, optional) – The target language. Defaults to ‘verilog’.
- path (str, optional) – Destination folder. Defaults to current dir.
- name (str, optional) – Top level instance name, and output file name. Defaults to self.top.__name__
- tb (bool, optional) – Specifies whether a test bench should be created. Defaults to True.
- trace (bool, optional) – Whether the testbench should dump all signal waveforms. Defaults to True.
- timescale (str, optional) – Defaults to ‘1ns/1ps’
-
sim
(**kwargs)[source]¶ Simulate the top function.
Parameters: - backend (str, optional) – Simulation runner. Available options are ‘myhdl’, ‘icarus’ and ‘modelsim’. Defaults to ‘myhdl’.
- hdl (str) – Target HDL for conversion before simulation.
- **kwargs – Optional arguments that
convert()
takes.
Returns: Generator sequence if the backend is myhdl,
myhdl.Cosimulation
object if the backend is a simulator.
-
Internals¶
uhdl.structures¶
Data structures(unrelated to hardware description) used internally by uhdl.
Changelog¶
Unreleased¶
- Python 3 support
run
has been split into asim
decorator and arun_sim
function
(2013-10-27)¶
First public version. Not available on PyPI anymore because of various issues.
- Features:
- Constructors: bits, randbits, create, Sig, Sigs, Clock, Reset
- Simulation: HW, run
- math: clog2, roundup